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Verilog HDL(°³Á¤ÆÇ) ±¤¹®°¢/À̽ÂÀº
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¹ßÇàÀÏ : 2022-01-15
ISBN | 9788970936840(897093684X) |
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Âʼö | 312ÂÊ |
Å©±â | 188 * 257 mm ÆÇÇü¾Ë¸² |
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- ±â¼ú/°øÇÐ > Àü±â/ÀüÀÚ > µðÁöÅÐ/Á¦¾î°øÇÐ > µðÁöÅнýºÅÛ
- ±â¼ú/°øÇÐ > ´ëÇб³Àç > ±â°è°øÇÐ
- ´ëÇб³Àç > ±â¼ú°øÇÐ > ±â°è°øÇÐ
µðÁöÅРȸ·Î ¼³°è¸¦ ½ÃÀÛÇÏ´Â ÀÔ¹®ÀÚµéÀÌ
ÀÌ Ã¥¿¡ ¾ð±ÞµÈ Verilog HDL ±â¼ú ¹æ¹ý¸¸À» »ç¿ëÇÏ¿© ȸ·Î ¼³°è°¡ °¡´ÉÇϵµ·Ï ¼³¸íÇÑ ±³Àç !
ÀÌ Ã¥¿¡ ¾ð±ÞµÈ Verilog HDL ±â¼ú ¹æ¹ý¸¸À» »ç¿ëÇÏ¿© ȸ·Î ¼³°è°¡ °¡´ÉÇϵµ·Ï ¼³¸íÇÑ ±³Àç !
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Chapter 01. µðÁöÅÐ ½Ã½ºÅÛ(Digital System)
1.1 µðÁöÅаú ¾Æ³¯·Î±×(Digital and Analog)
1.2 ºñÆ®, ¹ÙÀÌÆ®, ¿öµå(Bit, Byte, and Word)
1.3 ¼ö(Numbers)
1.4 ½ºÀ§Äª ¼ÒÀÚ(Switching Devices)
1.5 ³í¸® °ÔÀÌÆ®(Logic Gates)
1.6 ³í¸® ·¹º§(Logic Levels)
1.7 CMOS
1.8 FPGA¿Í ASIC
Chapter 02. ºÎ¿ï ´ë¼ö(Boolean Algebra)
2.1 °ø¸® (Axiom)
2.2 Á¤¸®(Theorem)
2.3 µå¸ð¸£°£ Á¤¸®(DeMorgan Theorem)
2.4 ³í¸®½Ä(Boolean Equation)
2.5 Ä«³ë¸Ê(Karnaugh Map)
Chapter 03. Verilog HDL
3.1 ¼Ò°³(Introduction)
3.2 ±âº» ¹®¹ý(Basics)
3.3 ¿¬»êÀÚ(Operators)
3.4 ¸ðµâ ¿¬°á(Instantiation)
3.5 ¸ðµ¨¸µ ·¹º§(Level of Modeling)
3.6 Å×½ºÆ® º¥Ä¡(Testbench)
3.7 ½Ã½ºÅÛ Å½ºÅ©(System Task)
Chapter 04. Á¶ÇÕȸ·Î(Combinational Logic)
4.1 °ÔÀÌÆ®(Gates)
4.2 ¸ðµâ(Module)
4.3 Á¶ÇÕȸ·Î ±â¼ú ¹æ¹ý(Combinational Logic Design)
4.4 µ¥ÀÌÅÍ Àü¼Û Á¶ÇÕȸ·Î(Data Logic)
4.5 »ê¼ú¿¬»ê Á¶ÇÕȸ·Î(Arithmetic Logic)
4.6 Á¶ÇÕȸ·Î Å×½ºÆ® º¥Ä¡(Testbench)
Chapter 05. ¼øÂ÷ȸ·Î(Sequential Logic)
5.1 ±â¾ï¼ÒÀÚ(Memory)
5.2 ?ºí·ÎÅ·°ú ³Íºí·ÎÅ·(Blocking and Non-blocking)
5.3 ?µ¿±â½Ä ¼øÂ÷ ȸ·Î(Synchronous Sequential Logic)
5.4 FSM(Finite State Machine)
5.5 FMS ±â¼ú ¹æ¹ý(FSM Design)
5.6 ½ÅÈ£µî Á¦¾î±â FSM(Traffic Signal Controller)
5.7 ½ÃÇÁÆ® ·¹Áö½ºÅÍ(Shift Register)
5.8 Verilog HDL ±â¼ú¹æ¹ý ¿ä¾à(Summary)
Chapter 06. ŸÀ̹Ö(Timing)
6.1 Á¶ÇÕȸ·Î ŸÀ̹Ö(Combinational Logic Timing)
6.2 ¼øÂ÷ȸ·Î ŸÀ̹Ö(Sequential Logic Timing)
6.3 ÀÔÃâ·Â ÇüÅÂ¿Í Å¸À̹Ö(Critical Path)
6.4 Verilog HDL¿¡¼ÀÇ µô·¹ÀÌ(Delay)
Chapter 07. IC¸¦ ÀÌ¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ½Ç½À(Digital System Design using IC)
7.1 ½Ç½À Àü¿¡ ¾Ë¾Æ¾ß ÇÒ °Íµé(Basics)
7.2 ¼¼±×¸ÕÆ® µðÄÚ´õ ¼³°è(Segment Decoder)
7.3 2ºñÆ® ´Ù¿î Ä«¿îÅÍ ¼³°è(2-bit Down Counter)
7.4 º¥µù¸Ó½Å Á¦¾î±â ¼³°è(Vending Machine)
7.5 IC¸¦ ÀÌ¿ëÇÑ µðÁöÅРȸ·Î ¼³°è Á¤¸®(Summary)
Chapter 08. Verilog HDLÀ» ÀÌ¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ½Ç½À(Digital System Design using Verilog HDL)
8.1 ¼¼±×¸ÕÆ® µðÄÚ´õ ¼³°è(Segment Decoder)
8.2 Verilog HDL ½Ã¹Ä·¹À̼Ç(Simulation)
8.3 FPGA ȸ·Î ±¸Çö(FPGA Implementation)
8.4 ¼¼±×¸ÕÆ® µð½ºÇ÷¹ÀÌ ÄÁÆ®·Ñ·¯ ¼³°è(Display Controller)
8.5 ½ºÅé¿öÄ¡ ¼³°è(Stopwatch)
8.6 ALU ¼³°è(Arithmetic Logic Unit)
8.7 UART ¼³°è(Universal Asynchronous Receiver and Transmitter)
8.8 ½ÃÇÁÆ® ·¹Áö½ºÅÍ(Shift Register)¸¦ ÀÌ¿ëÇÑ UART ¼³°è
8.9 ¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼ ¼³°è(Microprocessor)
ºÎ·Ï. ½Ç½Àº¸µå ¼³¸í¼ (User Manual)
1. SPL-Lab100 º¸µå °³¿ä(Overview)
2. ÀÔÃâ·Â(General User Input/Output)
1.1 µðÁöÅаú ¾Æ³¯·Î±×(Digital and Analog)
1.2 ºñÆ®, ¹ÙÀÌÆ®, ¿öµå(Bit, Byte, and Word)
1.3 ¼ö(Numbers)
1.4 ½ºÀ§Äª ¼ÒÀÚ(Switching Devices)
1.5 ³í¸® °ÔÀÌÆ®(Logic Gates)
1.6 ³í¸® ·¹º§(Logic Levels)
1.7 CMOS
1.8 FPGA¿Í ASIC
Chapter 02. ºÎ¿ï ´ë¼ö(Boolean Algebra)
2.1 °ø¸® (Axiom)
2.2 Á¤¸®(Theorem)
2.3 µå¸ð¸£°£ Á¤¸®(DeMorgan Theorem)
2.4 ³í¸®½Ä(Boolean Equation)
2.5 Ä«³ë¸Ê(Karnaugh Map)
Chapter 03. Verilog HDL
3.1 ¼Ò°³(Introduction)
3.2 ±âº» ¹®¹ý(Basics)
3.3 ¿¬»êÀÚ(Operators)
3.4 ¸ðµâ ¿¬°á(Instantiation)
3.5 ¸ðµ¨¸µ ·¹º§(Level of Modeling)
3.6 Å×½ºÆ® º¥Ä¡(Testbench)
3.7 ½Ã½ºÅÛ Å½ºÅ©(System Task)
Chapter 04. Á¶ÇÕȸ·Î(Combinational Logic)
4.1 °ÔÀÌÆ®(Gates)
4.2 ¸ðµâ(Module)
4.3 Á¶ÇÕȸ·Î ±â¼ú ¹æ¹ý(Combinational Logic Design)
4.4 µ¥ÀÌÅÍ Àü¼Û Á¶ÇÕȸ·Î(Data Logic)
4.5 »ê¼ú¿¬»ê Á¶ÇÕȸ·Î(Arithmetic Logic)
4.6 Á¶ÇÕȸ·Î Å×½ºÆ® º¥Ä¡(Testbench)
Chapter 05. ¼øÂ÷ȸ·Î(Sequential Logic)
5.1 ±â¾ï¼ÒÀÚ(Memory)
5.2 ?ºí·ÎÅ·°ú ³Íºí·ÎÅ·(Blocking and Non-blocking)
5.3 ?µ¿±â½Ä ¼øÂ÷ ȸ·Î(Synchronous Sequential Logic)
5.4 FSM(Finite State Machine)
5.5 FMS ±â¼ú ¹æ¹ý(FSM Design)
5.6 ½ÅÈ£µî Á¦¾î±â FSM(Traffic Signal Controller)
5.7 ½ÃÇÁÆ® ·¹Áö½ºÅÍ(Shift Register)
5.8 Verilog HDL ±â¼ú¹æ¹ý ¿ä¾à(Summary)
Chapter 06. ŸÀ̹Ö(Timing)
6.1 Á¶ÇÕȸ·Î ŸÀ̹Ö(Combinational Logic Timing)
6.2 ¼øÂ÷ȸ·Î ŸÀ̹Ö(Sequential Logic Timing)
6.3 ÀÔÃâ·Â ÇüÅÂ¿Í Å¸À̹Ö(Critical Path)
6.4 Verilog HDL¿¡¼ÀÇ µô·¹ÀÌ(Delay)
Chapter 07. IC¸¦ ÀÌ¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ½Ç½À(Digital System Design using IC)
7.1 ½Ç½À Àü¿¡ ¾Ë¾Æ¾ß ÇÒ °Íµé(Basics)
7.2 ¼¼±×¸ÕÆ® µðÄÚ´õ ¼³°è(Segment Decoder)
7.3 2ºñÆ® ´Ù¿î Ä«¿îÅÍ ¼³°è(2-bit Down Counter)
7.4 º¥µù¸Ó½Å Á¦¾î±â ¼³°è(Vending Machine)
7.5 IC¸¦ ÀÌ¿ëÇÑ µðÁöÅРȸ·Î ¼³°è Á¤¸®(Summary)
Chapter 08. Verilog HDLÀ» ÀÌ¿ëÇÑ µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ½Ç½À(Digital System Design using Verilog HDL)
8.1 ¼¼±×¸ÕÆ® µðÄÚ´õ ¼³°è(Segment Decoder)
8.2 Verilog HDL ½Ã¹Ä·¹À̼Ç(Simulation)
8.3 FPGA ȸ·Î ±¸Çö(FPGA Implementation)
8.4 ¼¼±×¸ÕÆ® µð½ºÇ÷¹ÀÌ ÄÁÆ®·Ñ·¯ ¼³°è(Display Controller)
8.5 ½ºÅé¿öÄ¡ ¼³°è(Stopwatch)
8.6 ALU ¼³°è(Arithmetic Logic Unit)
8.7 UART ¼³°è(Universal Asynchronous Receiver and Transmitter)
8.8 ½ÃÇÁÆ® ·¹Áö½ºÅÍ(Shift Register)¸¦ ÀÌ¿ëÇÑ UART ¼³°è
8.9 ¸¶ÀÌÅ©·ÎÇÁ·Î¼¼¼ ¼³°è(Microprocessor)
ºÎ·Ï. ½Ç½Àº¸µå ¼³¸í¼ (User Manual)
1. SPL-Lab100 º¸µå °³¿ä(Overview)
2. ÀÔÃâ·Â(General User Input/Output)
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